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lt8490 1 8490fa for more information www.linear.com/lt8490 typical application features description high voltage, high current buck-boost battery charge controller with maximum power point tracking (mppt) the lt ? 8490 is a buck-boost switching regulator battery charger that implements a constant-current constant- voltage (cccv) charging profile used for most battery types, including sealed lead-acid (sla), flooded, gel and lithium-ion. the device operates from input voltages above, below or equal to the output voltage and can be powered by a solar panel or a dc power supply. on-chip logic provides automatic maximum power point tracking (mppt) for solar powered applications. the lt8490 can perform automatic temperature compensation by sensing an external thermistor thermally coupled to the battery. status and fault pins containing charger information can be used to drive led indicator lamps. the device is available in a low profile ( 0.75mm) 7mm 11mm 64-lead qfn package. simplified solar powered battery charger schematic applications n v in range: 6v to 80v n v b at range: 1.3v to 80v n single inductor allows v in above, below, or equal to v b at n automatic mppt for solar powered charging n automatic temperature compensation n no software or firmware development required n operation from solar panel or dc supply n input and output current monitor pins n four integrated feedback loops n synchronizable fixed frequency: 100khz to 400khz n 64-lead (7mm 11mm 0.75mm) qfn package n solar powered battery chargers n multiple types of lead-acid battery charging n li-ion battery charger n battery equipped industrial or portable military equipment l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. lt8490 solar panel tg1 boost1 csnincspin v in cspout csnout extv cc av dd tempsense gatev cc intv cc sw1 bg1 csp csn status fault av dd bg2 sw2 boost2 tg2 gnd rechargable battery load thermistor + C 8490 ta01a av dd gatev cc gatev cc gatev cc v bat 8490 ta01b 0.5s/div v panel 6v/div i panel 1.36a/div back page application perturb & observe perturb & observe full panel scan maximum power point tracking downloaded from: http:///
lt8490 2 8490fa for more information www.linear.com/lt8490 pin configuration absolute maximum ratings v csp C v csn , v cspin C v csnin , v cspout C v csnout ................................... C 0.3v to 0.3v ss, clkout, csp, csn voltage .................. C 0.3v to 3v v c voltage (note 2) ................................... C 0.3v to 2.2v ldo33, v dd , av dd voltage .......................... C 0.3v to 5v rt, fbout voltage ....................................... C 0.3v to 5v imon_in , imon_out voltage .................... C 0.3v to 5v sync voltage ............................................ C 0.3v to 5.5v intv cc , gatev cc voltage ........................... C 0.3v to 7v v boost1 C v sw1 , v boost2 C v sw2 ................ C 0.3v to 7v swen, mode voltage ................................. C 0.3v to 7v srvo_fbin , srvo_fbout voltage ........... C 0.3v to 30v srvo_iin , srvo_iout voltage ................. C 0.3v to 30v fbin, shdn voltage ................................... C 0.3v to 30v csnin, cspin, cspout, csnout voltage .. C 0.3v to 80v v in , extv cc voltage .................................. C 0.3v to 80v sw1, sw2 voltage ..................................... 81v (note 5) boost1, boost2 voltage ........................ C 0.3v to 87v b g1 , b g2 , t g1 , t g2 ........................................... (note 4) iow, econ, clkdet voltage ......... C 0.3v to v dd + 0.5v sweno, status voltage ................ C 0.3v to v dd + 0.5v fbow, fbiw, fault voltage .......... C 0.3v to v dd + 0.5v vinr, fbor, iir, ior voltage ......... C 0.3v to v dd + 0.5v tempsense voltage ....................... C 0.3v to v dd + 0.5v chargecf g2 , chargecf g1 voltage ..................... C 0.3v to v dd + 0.5v operating junction temperature range lt8490 e (notes 1, 3) ......................... C 40 c to 125 c lt8490 i (notes 1, 3) .......................... C 40 c to 125 c storage temperature range ................. C 65 c to 150 c (note 1) top view ukj package 64-lead (7mm 11mm) plastic qfn 65 gnd fbir 1 fault 2 tempsense 3 v dd 4 fbow 5 fbiw 6 intv cc 7 swen 8mode 9 imon_in 10 shdn 11 csn 12 csp 13 ldo33 14 fbin 15 fbout 16 imon_out 17 v c 18 ss 19 clkout 20 52 nc51 status 50 iow49 sweno 48 econ46 v in 45 cspin44 csnin 42 cspout 41 csnout 40 extv cc 38 srvo_fbout37 srvo_iout 36 srvo_iin 35 srvo_fbin 33 boost1 64 ior63 chargecfg2 62 gnd 61 chargecfg1 60 nc 59 gnd 58 av dd 57 fbor56 clkdet 55 gnd 54 vinr 53 iir sync 21 rt 22 bg1 23 gatev cc 24 bg2 25 boost2 27 tg2 28 sw2 29 sw1 31 tg1 32 t jmax = 125c, ja = 34c/w exposed pad (pin 65) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8490eukj#pbf lt8490eukj#trpbf lt8490ukj 64-lead (7mm 11mm) plastic qfn C40c to 125c lt8490iukj#pbf lt8490iukj#trpbf lt8490ukj 64-lead (7mm 11mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. downloaded from: http:///
lt8490 3 8490fa for more information www.linear.com/lt8490 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c . v in = 12v , v dd = av dd = 3.3v, shdn = 3v unless otherwise noted. (note 3) parameter conditions min typ max units voltage supply and regulators v in operating voltage range (note 7) l 6 80 v v in quiescent current not switching, v extvcc = 0, v dd = av dd = float 2.65 4.2 ma v in quiescent current in shutdown v shdn = 0v 0 1 a v dd quiescent current i avdd + i vdd , v dd = av dd = 3.3v l 2.5 4 6.5 ma extv cc switchover voltage i intvcc = 20ma, v extvcc rising l 6.15 6.4 6.6 v extv cc switchover hysteresis 0.18 v ldo33 pin voltage 5ma from ldo33 pin l 3.23 3.295 3.35 v ldo33 pin load regulation i ldo33 = 0.1ma to 5ma C0.25 C1 % ldo33 pin current limit l 12 17.25 22 ma ldo33 pin undervoltage lockout ldo33 falling 2.96 3.04 3.12 v ldo33 pin undervoltage lockout hysteresis 35 mv switching regulator controlshdn input voltage high shdn rising to enable the device l 1.184 1.234 1.284 v shdn input voltage high hysteresis 50 mv shdn input voltage low device disabled, low quiescent current l 0.35 v shdn pin bias current v shdn = 3v v shdn = 12v 0 11 1 22 a a swen rising threshold voltage l 1.156 1.206 1.256 v swen threshold voltage hysteresis 22 mv mode pin thresholds discontinuous mode forced continuous mode l l 0.4 2.3 v v imon_out rising threshold for ccm operation mode = 0v l 168 195 224 mv imon_out falling threshold for dcm mode = 0v l 95 122 150 mv voltage regulation regulation voltage for fbout v c = 1.2v, extv cc = 0v l 1.193 1.207 1.222 v regulation voltage for fbin v c = 1.2v, extv cc = 0v l 1.184 1.205 1.226 v fbout pin bias current current out of pin 15 na fbin pin bias current current out of pin 10 na current regulation regulation voltage for imon_in and imon_out v c = 1.2v, extv cc = 0v l 1.187 1.208 1.229 v imon_in output current v cspin C v csnin = 50mv, v cspin = 5.025v v cspin C v csnin = 50mv, v cspin = 5.025v v cspin C v csnin = 0mv, v cspin = 5v l l 54 53 2.5 57 57 7 60 61 11.5 a a a imon_in over voltage threshold l 1.55 1.61 1.67 v imon_out output current v cspout C v csnout = 50mv, v cspout = 5.025v v cspout C v csnout = 50mv, v cspout = 5.025v v cspout C v csnout = 5mv, v cspout = 5.0025v v cspout C v csnout = 5mv, v cspout = 5.0025v l l 47.5 47 3.25 2.75 50 50 5 5 52.5 54.25 6.75 8 a a a a imon_out over voltage threshold l 1.55 1.61 1.67 v downloaded from: http:///
lt8490 4 8490fa for more information www.linear.com/lt8490 parameter conditions min typ max units switching regulator oscillator (osc1)switch frequency range syncing or free running 100 400 khz switching frequency, f osc r t = 365k r t = 215k r t = 124k l l l 102 170 310 120 202 350 142 235 400 khz khz khz sync high level for synchronization l 1.3 v sync low level for synchronization l 0.5 v sync clock pulse duty cycle v sync = 0v to 2v 20 80 % recommended min sync ratio, f sync /f osc 3/4 clkout output voltage high 1ma out of clkout pin 2.3 2.45 2.55 v clkout output voltage low 1ma into clkout pin 25 100 mv clkout duty cycle t j = C40c t j = 25c t j = 125c 22.7 44.1 77 % % % charging control status, fbow, fbiw, sweno, iow, econ output low voltage i ol = 5ma l 0.22 0.5 v status, fbow, fbiw, sweno, iow, econ output high voltage i oh = C5ma l 2.7 3.0 v fault output voltage low i ol = 0.5ma l 0.1 0.25 v fault output voltage high i oh = C0.1ma l 1.7 2.2 v power supply mode detection threshold (note 6) vinr pin falling l 155 174 mv power supply mode detection threshold hysteresis (note 6) vinr pin 29 mv minimum vinr voltage for start-up (note 6) not in power supply mode low power mode enabled low power mode disabled l l 380 213 395 225 410 237 mv mv high charging current threshold on ior (note 6) ior rising g econ rising l 168 195 224 mv low charging current threshold on ior (note 6) ior falling g econ falling l 95 122 150 mv minimum chargecfg1 % of av dd to disable stage 3 (note 6) temperature compensation enabled l 94 95 96 % maximum chargecfg1 % of av dd to disable stage 3 (note 6) temperature compensation disabled l 4 5 6 % minimum chargecfg2 % of av dd to disable time limits (note 6) wide valid t emperature range l 94 95 96 % maximum chargecfg2 % of av dd to disable time limits (note 6) narrow valid t emperature range l 4 5 6 % minimum tempsense % of av dd to detect battery disconnected (note 6) l 94.5 96 97.5 % v cspout C v csnout threshold for c/5 detection (note 6) v csxout common mode = 5.0v, r total from imon_out to ground = 24.3k 9 10 11 mv v cspout C v csnout threshold for c/10 detection (note 6) v csxout common mode = 5.0v, ior falling, r total from imon_out to ground = 24.3k 4.25 5 5.75 mv fbiw, fbow pwm frequency (osc2) 31.25 khz fbiw, fbow pwm resolution 8 bits status uart bit rate l 2160 2400 2640 baud internal a/d resolution 10 bits electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c . v in = 12v , v dd = av dd = 3.3v, shdn = 3v unless otherwise noted. (note 3) downloaded from: http:///
lt8490 5 8490fa for more information www.linear.com/lt8490 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: do not force voltage on the v c pin. note 3 : the lt8490 e is guaranteed to meet performance specifications from 0c to 125 c junction temperature. specifications over the C 40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8490 i is guaranteed over the full C 40 c to 125 c junction temperature range. note 4: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only, otherwise permanent damage may occur. note 5: negative voltages on the sw1 and sw2 pins are limited in the applications by the body diodes of the external nmos devices m2 and m3 or parallel schottky diodes when present. the sw1 and sw2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. note 6: these thresholds are measured by the internal a-d converter. the a-d reference voltage is av dd . av dd , v dd and an additional 2.8ma load are regulated by ldo33 to create the av dd reference for these measurements. the absolute threshold voltages will shift with corresponding changes in the av dd voltage. note 7: 10v minimum v in required for solar powered start-up if low power mode is enabled. downloaded from: http:///
lt8490 6 8490fa for more information www.linear.com/lt8490 typical performance characteristics status v oh and v ol (v dd = av dd = 3.3v) fault v oh and v ol (v dd = av dd = 3.3v) ldo33 load regulation (not connected to av dd and v dd ) imon output currents power supply mode charging lead acid battery "b t a = 25c, unless otherwise noted. |i fault | (ma) 0 v fault (v) 1 32 0 2 8490 g06 3 1 C40c 125c C40c 25c v oh v ol 125c 25c load current (ma) 0 ldo33 (v) 3.1 3.3 3.43.2 3 8 8490 g07 20 4 12 16 25c C40c 125c csxin-csxout (mv) C100 pin current (a) 0 175 200125 150100 50 7525 C25 0 50 8490 g08 200 C50 100 150 imon_out imon_in |i status | (ma) 0 v status (v) 1 32 0 15 8490 g05 20 5 10 C40c 125c 25c C40c 125c v oh v ol 25c stage 2 stage 1 stage 3 charging time (hours) 0 v bat (v) and i bat (a) 2.50 15.012.5 0 7.50 10.05.00 8490 g04 12 v bat back page application i bat v in = 36v fbout, fbin, imonin, imonout voltage rise vs power intv cc regulator power (w) 0 voltage rise (%) 0.2 1.00.6 0.80.4 0 0.5 8490 g09 2 1 1.5 intv cc regulated from v in intv cc regulated from extv cc solar powered charging lead acid battery "a solar powered charging lead acid battery "b solar powered charging lithium ion battery time of day 9am v bat (v) and i bat (a) 2.50 17.515.0 12.5 10.0 7.50 5.00 0 8490 g01 6pm partly cloudy stage some transients from full panel scans removed for clarity. v bat i bat sunset charging stage 0 3 back page application time of day 10am v bat (v) and i bat (a) charging stage 2.50 17.515.0 12.5 10.0 7.50 5.00 0 8490 g02 6pm v bat i bat cloudy day stage some transients from full panel scans removed for clarity. 0 sunset 3 back page application time of day 1pm v bat (v) i bat (a) 3028 26 24 20 8490 g03 5pm v bat partly cloudy stage 2 stage 1 0 2 4 6 8 10 i bat some transients from full panel scans removed for clarity. uart and status indicate < c/10 figure 34 application downloaded from: http:///
lt8490 7 8490fa for more information www.linear.com/lt8490 typical performance characteristics perturb and observe maximum power point tracking full panel scan single power peak full panel scanpartially shaded with dual power peaks panel voltage in low power mode panel voltage in low power mode maximum power point tracking perturb and observe perturb and observe t a = 25c, unless otherwise noted. 8490 g10 30s/div v panel 5v/div imon_out 500mv/div perturb & observe figure 34 application full panel scans 8490 g11 0.5s/div v panel 5v/div i mon_out 200mv/div figure 34 application 8490 g12 0.5s/div v panel 5v/div imon_out 100mv/div figure 34 application 8490 g13 5s/div v panel 6v/div imon_out 100mv/div figure 34 application rotate panel towards the sun. panel voltage and current are automatically adjusted to new max. 8490 g14 0.5s/div v panel 10v/div imon_in 500mv/div imon_out 500mv/div figure 34 application power peak 8490 g15 0.5s/div v panel 10v/div imon_in 200mv/div imon_out 200mv/div figure 34 application lower power peak max power peak 8490 g16 40ms/div v panel 5v/div swen 5v/div imon_out 50mv/div figure 34 application 10.6mv 10.4v 17.6v 3.3v 8490 g17 40ms/div v panel 5v/div swen 5v/div imon_out 50mv/div figure 34 application 10.6mv 10.1v 3.3v downloaded from: http:///
lt8490 8 8490fa for more information www.linear.com/lt8490 pin functions fbir (pin 1) : a/d input pin. connects to fbin pin to measure input feedback voltage. fault (pin 2) : fault pin. this pin generates an active high digital output that, when used with an led, provides a visual indication of a fault event. tempsense (pin 3) : a/d input pin. connects to a thermis - tor divider network for sensing battery temperature or a resistor divider if unused. this pin is frequently monitored for temperature compensation and enforcing temperature limits. v dd (pin 4) : control logic power supply pin. connect this pin to ldo33 and av dd . fbow (pin 5) : pwm digital output pin. connects to fbout through an rcr network to temperature compensate the battery voltage. fbiw (pin 6) : pwm digital output pin. connects to fbin through an rcr network to adjust the solar panel volt- age for mppt. intv cc (pin 7) : internal 6.35v regulator output pin. con - nects to the gatev cc pin. intv cc is powered from extv cc when the extv cc voltage is higher than 6.4v , otherwise intv cc is powered from v in . bypass this pin to ground with a minimum 4.7f ceramic capacitor. see switching configuration - mode pin for additional details.swen (pin 8) : switch enable pin. tie to the sweno pin. mode (pin 9) : mode pin. the voltage applied to this pin sets the operating mode of the switching regulator. tie this pin to intv cc to make discontinuous current mode active. tie this pin to ground to operate in discontinuous current mode for low battery charging currents and continuous current mode for high battery charging currents. do not float this pin. see switching configuration - mode pin for additional details. imon_in (pin 10) : input current monitor pin. the current out of this pin is proportional to the input current. see the applications information section for more information. shdn (pin 11) : shutdown pin. in conjunction with the uvlo (undervoltage lockout) circuit, this pin is used to enable/disable the chip. do not float this pin. csn (pin 12) : the ( C ) input to the inductor current sense and reverse current detect amplifier. csp (pin 13) : the (+) input to the inductor current sense and reverse current detect amplifier. the v c pin voltage and built-in offsets between the csp and csn pins set the current trip threshold. ldo33 (pin 14) : 3.3v regulator output. this supply provides power to the v dd and av dd pins. bypass this pin to ground with a minimum 4.7f ceramic capacitor. fbin (pin 15) : input feedback pin. this pin is connected to the input error amplifier input. fbout (pin 16) : output feedback pin. this pin connects the error amplifier input to an external resistor divider from the output. imon_out (pin 17) : output current monitor pin. the current out of this pin is proportional to the average out-put current. see the applications information section for more information. v c (pin 18) : error amplifier output pin. tie the external compensation network to this pin.ss (pin 19) : soft-start pin. place 100nf of capacitance from this pin to ground. upon start-up, this pin will be charged by an internal resistor to 2.5v. clkout (pin 20) : switching regulator clock output pin. clkout will toggle at the same frequency as the switch - ing regulator oscillator (o sc1 on the block diagram) or as the sync pin, but is approximately 180 out-of-phase. clkout can also be used as a temperature monitor of the switching regulator since the clkout duty cycle varies linearly with the junction temperature of the switching regulator. it is connected to clkdet through an rc filter. the clkout pin can drive capacitive loads up to 200pf. sync (pin 21) : to synchronize the switching frequency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock needs to exceed 1.3v , and the low level should be less than 0.5v . drive this pin to less than 0.5v to revert to the internal free-running clock (osc1 in the block diagram). downloaded from: http:///
lt8490 9 8490fa for more information www.linear.com/lt8490 pin functions rt (pin 22) : timing resistor pin. adjusts the switching regulator frequency (o sc1 ) when sync is not driven by a clock. place a resistor from this pin to ground to set the free-running frequency of o sc1 . do not float this pin. bg1 , b g2 (pin 23/pin 25) : bottom gate drive. drives the gates of the bottom n-channel mosfets between ground and gatev cc . gatev cc (pin 24) : power supply for gate drivers. must be connected to the intv cc pin. do not power from any other supply. locally bypass to ground. boost1, boost2 (pin 33/pin 27) : boosted floating driver supply. the (+) terminal of the bootstrap capacitor con - nects here. the boost1 pin swings from a diode voltage below gatevcc up to v in + gatev cc . the boost2 pin swings from a diode voltage below gatev cc up to v bat + gatev cc . tg1 , t g2 (pin 32/pin 28) : top gate drive. drives the top n-channel mosfets with voltage swings equal to gatev cc superimposed on the switch node voltages.sw1, sw2 (pin 31/pin 29) : switch nodes. the ( C ) terminal of the bootstrap capacitors connect here.srvo_fbin (pin 35) : open-drain logic output. this pin is pulled to ground when the input voltage feedback loop is active. this pin is unused for most lt8490 applications and can be floated.srvo_iin (pin 36) : open-drain logic output. this pin is pulled to ground when the input current feedback loop is active. this pin is unused for most lt8490 applications and can be floated.srvo_iout (pin 37) : open-drain logic output. this pin is pulled to ground when the output current feedback loop is active. this pin is unused for most lt8490 applications and can be floated. srvo_fbout (pin 38) : open-drain logic output. this pin is pulled to ground when the output voltage feedback loop is active. this pin is unused for most lt8490 applications and can be floated. extv cc (pin 40) : external v cc input. when extv cc ex - ceeds 6.4v (typical), int v cc will be powered from this pin. when extv cc is lower than 6.22v (typical), intv cc will be powered from v in . see switching configuration - mode pin for additional details.csnout (pin 41) : the ( C ) input to the output current sense amplifier. cspout (pin 42) : the (+) input to the output current sense amplifier. this pin and the csnout pin measure the voltage across the sense resistor to provide the output current signals. csnin (pin 44) : the ( C ) input to the input current sense amplifier. this pin and the cspin pin measure the voltage across the sense resistor to provide the instantaneous input current signals. cspin (pin 45) : the (+) input to the input current sense amplifier. v in (pin 46) : main input supply pin. must be bypassed to local ground plane.econ (pin 48) : digital output pin. optional control output signal used to disconnect extv cc from the battery when the average charge current drops below a predetermined threshold. sweno (pin 49) : digital output pin. connect to swen. enables the switching regulator. a 200k pull-down resis - tor is required from this pin to ground.iow (pin 50) : digital output pin. connects to imon_out through a resistor. by switching the pin between logic low and high impedance, the total r imon_out changes, which changes the output current limit. status (pin 51) : digital output pin. when used with an led, this signal provides a visual indication of the progress of the charging algorithm. in addition, status transmits two uart bytes (8 bits, no parity, one stop bit, 2400 baud) every 3.5 seconds (typical), which indicates status and fault information. iir (pin 53) : a/d input pin. connects to imon_in to read input current. used to manage mppt. downloaded from: http:///
lt8490 10 8490fa for more information www.linear.com/lt8490 vinr (pin 54) : a/d input pin. connects to resistive divider on vin to measure input voltage. used to manage mppt and start-up. clkdet (pin 56) : a/d input pin. connects to clkout through an rc filter to detect the duty cycle of clkout. used to manage start-up. fbor (pin 57) : a/d input pin. connects to fbout pin to read charger output voltage. used to manage the charg - ing algorithm.av dd (pin 58) : a/d positive reference pin. tie this pin to v dd and ldo33. pin functions chargecfg1 (pin 61) : a/d input pin. used to configure the float voltage, temperature compensation and enable stage 3 charging. chargecfg2 (pin 63) : a/d input pin. used to configure time limits and the valid battery temperature range. ior (pin 64) : a/d input pin. connects to imon_out pin to read the charger output current. used to manage the charging algorithm. gnd (exposed pad 65 and pins 55, 59, 62) : ground. tie directly to local ground plane.nc (pins 52, 60): not connected. downloaded from: http:///
lt8490 11 8490fa for more information www.linear.com/lt8490 block diagram fbow 5 2.5v 1.234v 8490 bd v in adc av dd av dd av dd nc 1.208v 1.208v 1.207v ntc adc av dd adc av dd adc av dd av dd adc av dd adc av dd adc av dd control, charging, mppt logic buck,boost logic uv_gatev cc uv_v in nc start-up and fault logic osc1 1.205v oi_out uv_intv cc oi_in ot uv_ldo33 10 10 10 10 10 10 10 10 10 +C a5 +C ea1 +C a7 +C ea2 +C a8 +C a9 + C + C +C ea3 fbin 15 shdn 11 sync 21 rt 22 clkout 20 clkdet 56 swen 8 sweno 49 srvo_iin 36 csnin 44 cspin 45 imonin 10 iir 53 vinr 54 ss 19 v in 46 mode 9 csn 12 csp 13 srvo_fbin 35 srvo_fbout 38 fbout 16 econ 48 av dd 58 v dd 4 srvo_iout 37 tempsense 3 fbiw 6 fbir 1 chargecfg1 61 chargecfg2 63 adc av dd fbor 57 adc av dd ior 64 imonout iow 17 50 csnout 41 cspout 42 intv cc 7 ldo33 14 v c 18 tg2 28 sw2 29 bg2 25 bg1 23 extv cc 40 gatev cc 24 v bat pwm pwm 3.3v reg ncnc reg 6.35v reg 6.4v 6.35v reg 305k internal supply1 internal supply2 +C ea4 boost2 27 tg1 32 boost1 33 sw1 31 osc2 solar panel +C rechargeable battery +C gnd 55 status 51 fault 2 C + a6 av dd av dd figure 1. block diagram downloaded from: http:///
lt8490 12 8490fa for more information www.linear.com/lt8490 operation overview the lt8490 is a powerful and easy to use battery charging controller with automatic maximum power point tracking (mppt) and temperature compensation. the lt8490 is based on the lt8705 buck-boost controller with additional battery charging and mppt control functions. refer to the lt8705 data sheet for more detailed information about the switching regulator portions of the lt8490 . several refer - ence applications are included in this data sheet to simplify system design. many batter y charging applications can be implemented using one of the reference applications with little or no modification required. configuration for the various charging parameters is implemented in the hard - ware. no software or firmware development is required. the lt8490 includes four different forms of regulation : output current, input current, input voltage and output voltage ( ea1-ea4 respectively as shown in figure 1). whichever form of regulation requires the lowest voltage on the v c pin limits the commanded inductor current. when powered by a solar panel, the mppt function uses input voltage regulation to locate and track the maximum power point of the panel. input current regulation is used to limit the maximum current drawn from the input supply. the output current regulation limits the battery charging current, and the output voltage regulation is used to set the maximum battery charging voltage. the lt8490 offers user configurable timers that can be enabled with the appropriate resistor divider on the chargecfg2 pin. if a timer has been set and expires, the lt8490 will halt charging and communicate this through the status and fault pins. options for automatic restart of the charge cycle are discussed later in the automatic charger restart and fault recovery section. the lt8490 also includes a tempsense pin, which can be connected to an ntc resistor divider network ther - mally coupled to the battery pack. when connected, the tempsense pin can provide temperature compensated charging and/or can be used to disable charging when the batter y is outside of safe temperature limits. the presence of the ntc resistor can also give an indication to the charger if the batter y is connected or not. the lt8490 also provides charging status and fault indica - tors through the status and fault pins. the behavior of these pins is described in the sta tus and fault indicators section.battery charging algorithm the lt8490 implements a cccv charging algorithm. the idealized charging profile is shown in figure 2 and assumes constant temperature and adequate input power. as battery temperature and illumination conditions on the panel change, the actual current and voltage seen by the battery will vary accordingly. after start-up, the lt8490 frequently measures the bat - tery voltage and charging current to determine the proper charging stage. figure 2. typical battery charging cycle 8490 f01 charging time stage 0 trickle charge stage 1 constant current stage 2 constant voltage stage 3 reduced constant voltage stage 3 voltage limit stage 2 voltage limit maximum charging current (c) charging current battery voltage (optional) v s3 v s2 downloaded from: http:///
lt8490 13 8490fa for more information www.linear.com/lt8490 operation stage 0 : in stage 0 (reduced constant-current/trickle charge) the lt8490 charges the battery with a hardware configurable reduced constant current. this trickle charge stage occurs for battery voltages between 35% to 70% (typical) of the stage 2 voltage limit (v s2 ). stage 1 : in stage 1 (full constant-current) the lt8490 charges the battery with a hardware configurable constant current equal to or higher than in stage 0. this constant current stage occurs for battery voltages between 70% to 98% (typical) of the stage 2 voltage limit. this charging stage is often referred to as bulk charging. this charg - ing stage will be called stage 1 for the remainder of this document. st age 2 : in stage 2 (constant-voltage) the lt8490 charges the battery with a hardware configurable constant voltage. this constant voltage stage occurs for battery voltages above 98% (typical) of the stage 2 voltage limit. this charging stage is often referred to as float charging for lithium-ion batteries and absorption charging for lead-acid batteries. to avoid confusion, this charging stage will be called stage 2 for the remainder of this document. if the optional stage 3 is enabled, the lt8490 will proceed from stage 2 to stage 3 when the charging current drops below c/10. other conditions for exiting stage 2 depend on whether time limits are enabled for the charger. see the charging time limits section for more details about stage 2 termination. stage 3 (optional) : stage 3 is optional as configured with the chargecf g1 pin. in stage 3 the lt8490 charges the battery with a hardware configurable reduced constant voltage. this charging stage is often referred to as float charging in lead-acid battery charging. this charging stage will be called stage 3 for the remainder of this document. charging will automatically restart if, during stage 3, the charging current exceeds c/5 or the battery voltage falls below 96% (typical) of the stage 3 voltage limit (v s3 ). in addition, an optional time limit can be enabled to terminate charging in stage 3. see the charging time limits section for more details about stage 3 termination. table 1. description of lt8490 charging stages stage name method duration 0 trickle charge constant current at a configured fraction of full charge current until battery voltage rises above v s0 (70% of stage 2 voltage limit) optional max time limit 1 constant current constant full charge current until battery voltage rises above v s1 (98% of stage 2 voltage limit) optional max time limit for stage 1 + stage 2 2 constant voltage constant voltage until charging current falls below c/10 or optional indefinite charging optional max time limit for stage 1 + stage 2 3 (optional) reduced constant voltage constant voltage at a configured fraction of stage 2 constant voltage until batter y v oltage falls below 96% of v s3 (stage 3 voltage limit - configurable) or charging current rises above c/5 optional max time limit. the same duration as the stage 1 + stage 2 time limit. maximum power point tracking when powered by a solar panel, the lt8490 employs a pro - prietary perturb and observe algorithm for identifying the maximum power point. this algorithm provides accurate mpp t for slow to moderate changes in panel illumination. the panel is also scanned periodically to avoid settling on a false maximum power point for long periods of time, in the case of non-uniform panel illumination. fault conditions the lt8490 can indicate the presence of a fault condi - tion through the status and fault pins. these faults include : battery undervoltage, battery overtemperature, battery under temperature and timer expiration. follow - ing a fault, the lt8490 will discontinue charging until the fault condition is removed, at which point it will continue or restart the charging cycle. see the automatic charger restart and fault recovery section for more information. downloaded from: http:///
lt8490 14 8490fa for more information www.linear.com/lt8490 applications information input voltage sensing and modulation network the passive component network shown in figure 3 is re - quired to properly measure and modulate the input supply voltage. this network is required whether the supply is a solar panel or a dc voltage sour ce. due to the granularity of standard resistor values, simply rounding the calculated results to their nearest standard values may result in unwanted errors. consider using multiple resistors in series to more closely match the calculated results. other wise, use standard resistor values and check the final results with the following equations: v x2 = 1.205 ? r fbin1 r daci1 + r daci2 + r fbin1 r fbin2 ?? ? ?? ? + 1 ?? ? ?? ? v x2 indicates the actual v max using the selected resis - tors. make sure this result is greater than or equal to the desired v max for the application. v x1 = v x2 ? 3.3 ? r fbin1 r dac1 + r dac2 ?? ? ?? ? v x1 should be as close to 6v as possible. iterations may be required to determine the best standard resistor values. table 2 shows good sets of standard value components for maximum input voltages of 20v, 40v, 60v and 80v. iterative calculations were required to select these values that achieve the best overall results. table 2. input feedback network vs panel voltage v max (v) r fbin1 (k) r fbin2 (k) r daci1 (k) r daci2 (k) c daci (nf) 20 95.3 8.45 3.4 19.1 270 40 107 4.87 1.69 8.66 560 60 105 3.24 1.05 5.36 1000 80 133 3.09 1.05 4.87 1000 as discussed later in dc supply powered charging, ar - bitrarily setting v max to 80v may not result in the best operation of the lt8490 for all conditions, particularly at low input voltages. be sure to give proper consideration to the required voltage range for each application. solar powered charging vinr divider network : the lt8490 can be powered by a solar panel or a dc power supply. as discussed later in dc supply powered charging, the vinr pin must be pulled low when being powered by a dc supply. otherwise, vinr must be connected to the resistor divider network as shown in figure 4. figure 3. input feedback resistor network 8490 f03 lt8490 gnd v in v in r daci1 c daci fbirfbin fbiw r daci2 r fbin1 r fbin2 choosing the components requires knowing the maxi - mum panel open-circuit voltage (v ocmax ) as well as the maximum dc input supply voltage (v dcmax ) desired (see the dc supply powered charging section for more information). v ocmax typically occurs at cold temperatures and should be specified in the panel manufacturer s data sheet. use the following equations to determine proper component values: r fbin1 = 100k ? 1 + 4.470v v max ? 6v ?? ? ?? ? 1 + 5.593 v max ? 6v ?? ? ?? ? ?? ?? ? ? ?? ?? ? ? r daci2 = 2.75 ? r fbin1 v max ? 6v ?? ? ?? ? r fbin2 = 1 1 100k ? r fbin1 ?? ? ?? ? ? 1 r daci2 ?? ? ?? ? r daci1 = 0.2 ? r daci2 c daci = 1 1000 ? r daci1 f where v max is the greater of v ocmax and v dcmax with some additional margin. these resistors should have a 1% tolerance or better. downloaded from: http:///
lt8490 15 8490fa for more information www.linear.com/lt8490 applications information the lt8490 uses this divider network to measure abso - lute panel voltage (as part of its maximum power point calculations) and to check for adequate input voltage to operate the charger. these resistors should have a 1% tolerance or better . timer termination disabled : when powered by a solar panel, the timer termination option (see the charging time limits section for more detail) is automatically dis - abled. this is due to the inability to guarantee full charging current during the entire charging cycle in cases where the panel illumination conditions change. in addition, the timers can reset if all power to the charger is lost due to insufficient lighting. this makes the use of timer termina - tion potentially unreliable in solar powered applications.c/10 detection : when powered by a solar panel, charg - ing current may drop below c/10 because the battery is approaching full charge, or because the solar panel has insufficient lighting. if sufficient panel power is available, the lt8490 can determine if the charging current has dropped below c/10 due to the battery approaching full charge. in this case, the charger will proceed from stage 2 to the next appropriate stage. if the lt8490 is able to de - termine that the charging current has dropped below c/10 due to insufficient panel power, the charger will continue operating in stage 2. minimum panel voltage requirement : a minimum panel voltage of 6v is required to operate the charger. however, higher panel voltages are required in various other cases. figure 4. vinr resistor divider circuit 8490 f04 lt8490 gnd v in v in vinr 196k8.06k 1. low power mode enabled : low power mode al - lows additional power to be recovered from the solar panel under very weak lighting conditions. when low power mode is enabled, the panel voltage must initially exceed 10v (typical C as measured through the vinr pin) before the charger will attempt to charge the bat - tery. read the optional low power mode section for more details. 2. low power mode disabled : if low power mode is disabled the charger will attempt to charge the battery as long as the panel is above 6v . however, if sufficient panel current is not detected the lt8490 will temporarily stop charging. the charger will check for sufficient panel current at 30 second intervals (typical) or will check sooner if the lt8490 detects either a significant rise in panel voltage or a significant fall in battery voltage. 3. low input voltage effects : figure 5 shows the minimum input voltage, below which the maximum charging current can be reduced. this limit is a function of the input v max as discussed previously in the input voltage and modulation network section. maximum charging current can reduce as fbin gets closer to its regulation voltage of 1.205v (typical). this is not normally a significant issue unless 1) the charger is powered by a low voltage dc power supply or 2) a low voltage panel is used with a charger that was configured for a much higher voltage panel. the farther that v in is below the normal configuration line in figure 5 the more the current can reduce. figure 5. minimum full charging current v in voltage v max (v) 0 0 5 10 15 minimum full-charging current v in voltage (v) 20 25 20 40 60 10 30 50 70 80 8490 f05 normal configuration dc supply only with fbin = ldo33 downloaded from: http:///
lt8490 16 8490fa for more information www.linear.com/lt8490 applications information when v in is powered by a dc voltage supply, main - tain v in higher than the normal configuration line in figure 5. operating v in below this line can reduce the maximum charging current and the v s2 and v s3 charging voltages. if v in is never going to be supplied by a solar panel then fbin can be disconnected from fbir (see figure 3) and reconnected to the ldo33 pin. this allows the charger to operate with v in as low as 6v with no charging current or voltage reduction. when using a solar panel supply, choose a panel having a maximum open-circuit voltage (v oc ) close to v max (discussed in the prior input voltage sensing and modulation network section). the maximum power point voltage is typically well above the voltage limit in figure 5 and current limiting is rarely an issue. avoid using solar panels that operate dramatically below v max , particularly if the maximum power point voltage is typi - cally below the normal configuration line in figure 5. dc supply powered chargingselecting power suppl y mode : when powered by a dc voltage source, the vinr pin must be pulled below 174mv (typical) to activate power supply mode. this disables unnecessary solar panel functions and allows the lt8490 to operate properly from a dc voltage source. if the application is never powered by a solar panel, vinr can be grounded. if the application is only powered by a solar panel, then connect vinr as shown in figure 4. otherwise, see the optional dc supply detection circuit section for a method to pull down the vinr pin when a dc supply is detected. minimum input voltage requirement : when power supply mode is enabled, the lt8490 will operate from an input as low as 6v . however, charging current capability can become limited at low input voltages depending on the v max voltage used to select the input voltage sensing network (see previous input voltage sensing and modula - tion network section). figure 5 shows the minimum input supply voltage required, below which charging current can become less than the maximum output current limit. if the lt8490 is powered by a dc supply only, the minimum input voltage shown in figure 5 can be reduced to 6v by figure 6. load connection to battery in lt8490 application (1) disconnecting fbin from fbir and (2) connecting the fbin pin directly to ldo33. input current limiting : input current limiting should be considered when using dc power supplies. this is discussed later in the input current limiting section. in situ battery charging the lt8490 can be used to charge a battery while the battery is powering a load. the load should be directly connected to the battery terminals as shown in figure 6. the variable nature of some loads can make charg - ing times unpredictable. due to this unpredictability it is recommended that charging time limits be disabled (see charger configuration C chargecf g2 pin section for more information). because a load connected to the battery may draw more power than provided by the charger, the battery may discharge while the lt8490 is charging the battery. if this case occurs and the battery voltage falls below 31% (typical) of the stage 2 voltage limit, the undervoltage fault will become active and the charger will halt until the battery voltage rises above 35% (typical) of the stage 2 voltage limit. consider automatically disabling the load if the battery depletes below an unacceptably low voltage. the arrow in figure 6 shows the proper disconnect point if removing the battery from the charger in an in situ battery charging application. this disconnect point is specified because the lt8490 is not designed to provide power directly to a load without the presence of a battery. 8490 f06 lt8490 based charger cable to/from charger v bat +C load downloaded from: http:///
lt8490 17 8490fa for more information www.linear.com/lt8490 applications information stage voltage limits the stage 2 voltage limit (v s2 ) is the maximum battery charging voltage. the voltage limits for stages 0, 1 and 3 are all related to the stage 2 limit as shown in table 3 and figure 11. if temperature compensated charging is enabled, then v s2 will change with temperature as shown in figure 13. as such, the limits for the other stages will also change with temperature since they are a constant proportion of v s2 . table 3. typical charging stage voltage thresholds stage transition v b at rising or falling typical v b at /v s2 typical v b at /v s3 v bat undervoltage fault stage 0 rising 35% C stage 0 stage 1 rising 70% C stage 1 stage 2 rising 98% C stage 3 stage 0 falling C 96% stage 2 stage 1 falling 95% C stage 1 stage 0 falling 66% C stage 0 v bat undervoltage fault falling 31% r fbout2 is often chosen between 4.99k? and 49.9k?. choosing higher values for r fbout2 reduces the amount of current draw from the battery through the feedback network. r fbout1 = r fbout2 ? v s2 ? 1.2411.211 ? 0.128 ?? ? ?? ? ? 1 ?? ? ?? ? r daco2 = r fbout1 ? r fbout2 ? 0.833 r fbout2 ? v s2 ? 1.2411.211 ?? ? ?? ? ? r fbout2 ? r fbout1 r daco1 = 0.2 ? r daco2 c daco = 1 500 ? r daco1 f for greater charging voltage accuracy, it is recommended that 0.1% tolerance resistors be used for the output feed - back resistor network. due to the granularity of standard resistor values, simply rounding the calculated results to their nearest standard values may result in unwanted errors. consider using multiple resistors in series to match the calculated results. other wise, use standard resistor values and check the final results with the following equations. v x3 = r fbout1 r daco1 + r daco2 ?? ? ?? ? ? x ? 1.89 ( ) where x = 1.211 ? 1 + r daco1 + r daco2 r fbout2 ?? ? ?? ? + r daco1 + r daco2 r fbout1 ?? ? ?? ? ?? ? ?? ? v x3 indicates the actual 25c v s2 voltage using the se - lected resistors. n1 = x ? 1.89 x ? 3.3 n1 should be as close as possible to 1.22. n2 = 1 ? 1.89 x n2 should be as close as possible to 0.805. iterations may be required to determine best standard resistor values. figure 7. output feedback resistor network 8490 f07 lt8490 gnd v bat r daco2 c daco fbor fbout fbow r daco1 r fbout1 r fbout2 setting the stage 2 voltage limit : the resistor network shown in figure 7 is used to set the stage 2 volt - age limit. battery manufacturers typically call for a higher stage 2 voltage limit than the nominal batter y voltage. for example, a 12v lead-acid battery used in automotive applications commonly has a stage 2 charging voltage limit of 14.2v . if temperature compensated charging will be used (see temperature measurement, compensation and fault section) then use the 25c value for v s2 in the equations below. downloaded from: http:///
lt8490 18 8490fa for more information www.linear.com/lt8490 table 4 shows good sets of standard value components for charging nominal battery voltages of 12v, 24v, 36v, 48v and 60v . iterative calculations were required to select these values that achieve the best overall results. table 4. standard value output feedback network vs output regulation voltage battery voltage target v s2 (v) r fbout1 (k) r fbout2 (k) r daco1 (k) r daco2 (k) c daco (nf) 12 14.2 274 23.2 26.1 124 82 24 28.4 487 20 28 107 68 36 42.6 787 21 22.6 121 100 48 56.8 1000 20 22.6 115 100 60 71.0 866 13.7 13.3 80.6 150 setting the stage 3 voltage limit : when enabled, stage 3 charging maintains the battery voltage at 85% to 99% of v s2 . this proportion is adjustable and is discussed in the charger configuration C chargecf g1 pin section. battery undervoltage limit : upon start-up, the lt8490 checks for battery voltage above 35% (typical) of the stage 2 voltage limit. if the battery voltage is less than this, charging will not start and a battery undervoltage fault will be indicated on the fault pin. charging will begin after the battery voltage rises above 35% (typical) of the stage 2 voltage limit. if the battery voltage subsequently falls below 31% (typical), charging will again stop and the fault will be indicated on the fault and status pins. charge current limiting the maximum charging current is configured with the output current limiting circuit. the output current is sensed through r sense2 and converted to a proportional current flowing out of the imon_out pin (see figure 8). applications information figure 8. output current regulation loop imon_out voltages above 1.208v (typical) cause v c to reduce due to ea1 , and thus limit the output current. iow is either driven to ground or floated depending on charg - ing conditions. this allows the current limit for stage 0 (i out(maxs0) ) to be set independently of the remaining stages (i out(max) ) with proper selection of r iow and r imon_out . use the following equations to configure the charging current limits: r sense2 = 0.0497 i out(max) r imon _ out = 1208 i out(maxs0) ? r sense2 r iow = 24.3k ? r imon _ out r imon _ out ? 24.3k r ior = 3.01k c imon _ out = read below where i out(max) is the maximum charging current in amps, i out(maxs0) is the maximum trickle charging current in stage 0 and i out(maxs0) is no greater than i out(max) . for cases where i out(max) = i out(maxs0) , it is ok to exclude r iow and float the i ow pin. i out(maxs0) must be at least 20% of i out(max) . 8490 f08 lt8490 r imon_out c imon_out fault control C + ea1 C + 1.208v 1.61v iow ior v c imon_out to battery csnout cspout from controller v out1 + C r sense2 output current r ior 3.01k r iow g m = 1m a6 downloaded from: http:///
lt8490 19 8490fa for more information www.linear.com/lt8490 applications information c imon_out reduces imon_out ripple and stabilizes the con - stant charging current control loop. reducing c imon_out improves stability and minimizes inductor current over - shoot that can occur if a discharged battery is quickly disconnected then reconnected to the charger . however , this is at the expense of increased imon_out ripple that can introduce more noise into the adc measurements. the higher frequency pole created at imon_out must be adequately separated from the lower frequency pole at the v c pin for proper stability. a c imon_out capacitor in the range of 4.7nf to 22nf is adequate for most applications. input current limiting solar panel supply : solar panels are inherently current limited and may not be able to provide maximum charging power at the lowest input voltages. the lt8490 uses its mppt algorithm to sweep the panel voltage as low as 6v to find the maximum power point. make sure that the input current limit is set higher than the maximum panel current capability, plus at least 20% to 30% margin, in order to achieve the maximum charging capability of the system. in addition, note that the lt8490 uses the same circuit (shown in figure 9) to measure the input current as to limit it. the input current is measured by an a/d conversion of the iir pin voltage which is connected to imon_in and is proportional to input current. the digitized input current is used to locate the maximum power point of the solar panel. setting a higher input current limit reduces the resolution of the digitized reading of the input current. avoid setting the input current limit dramatically higher than necessary, as this may affect the accuracy of the maximum power point calculations. dc power supply : when charging a battery at maxi - mum current, and thus power, a low voltage supply must provide more current than a high voltage supply. this can be seen by equating output power to input power, less some efficiency loss. v in ? i in ? = v bat ? i bat or i in(max) = v bat ? i bat(max) v in(min) ? figure 9. input current regulation loop where the efficiency factor is typically between 0.95 and 0.99. when powered by a dc supply, appropriate input cur - rent limiting is recommended for supplies that might (1) become overloaded as the supply ramps up or down through 6v or (2) provide more input current than the charger components can tolerate. setting the input current limit : the input current is sensed through r sense1 as shown in figure 9. the current through r sense1 is converted to a voltage on the imon_in pin according to the following equation: v imon _in = i in ? r sense1 1000 + 7a ?? ? ?? ? ? r imon _in ? ? ? ? ? ? v imon_in voltages exceeding 1.208v (typical) cause the v c voltage to reduce, thus limiting the input current. r imon_in should be 21k 1% or better. using this information, the appropriate value for r sense1 can be calculated using the following equation: r sense1 = 1000 ? 1.208v 21k ? 7a ?? ? ?? ? i in(max) = 0.0505 i in(max) where i in(max) is the maximum input current limit in amps. r sense1 values greater than 25m are not recommended. 8490 f09 lt8490 21k r imon_in c imon_in fault control C + ea2 C + 1.208v 7mv 1.61v iir v c imon_in to remainderof system csnin cspin from solar panel or dc power supply + C r sense1 output current g m = 1m a7 + C downloaded from: http:///
lt8490 20 8490fa for more information www.linear.com/lt8490 c imon_in reduces imon_in ripple and stabilizes the input current limit control loop. reducing c imon_in improves sta - bility and minimizes possible inductor current overshoot. however, this is at the expense of increased imon_in ripple that can introduce more noise into the adc measurem ents. the higher frequency pole created at imon_in must be adequately separated from the lower frequency pole at the v c pin for proper stability. a c imon_in capacitor of 4.7nf to 22nf is adequate for most applications.input and output current sense filtering the c sx and r sx current sense filtering shown in figure 10 can improve the accuracy of the input and output current measurements at low average current levels. amplifiers a7 and a8 (figures 8 and 9) can only amplify positive r sense voltages. although the average r sense voltage is always positive, the voltage ripple at low average current levels may contain negative components that are averaged out by the filter. recommended values for r s1 , r s2 and c s1 , c s2 are 10 and 470nf. c c1 and c c2 may be required, depending on board layout, to reduce common mode noise that may reach the lt8490 pins. 100nf ceramic capacitors, with the appropriate volt - age ratings, work well in most cases. be sure to place all of the filter components (c sx , r sx , c cx ) close to the lt8490 for best performance. finally, note that a small voltage drop (typically ~0.25mv per 10 ) will occur across r s1 and r s2 due to the input bias currents of csnout and csnin. this represents a ~ 0.5% reduction in the maximum current limit which typi - cally occurs with ~ 50mv across r sense . the c/10 threshold (typically when 5mv is measured across cspout and csnout) will also reduce to c/10.5 due to the 0.25mv drop across r s2 . applications information charger configuration C chargecfg1 pinthe chargecf g1 pin is a multifunctional pin as shown in figure 11. set this pin using a resistor divider totaling no less than 100k to the av dd pin (see the typical applica - tions section for examples). the voltage on chargecf g1 , as a percentage of a v dd , makes the selections discussed below. avoid setting the divider ratio directly at any of the inflection points on figure 11 (e.g. 5%, 45%, 50%, 55% or 95%) enable/disable temperature compensated volt - age limits : setting the chargecf g1 pin in the upper half of the voltage range ( > 50%) enables battery voltage temperature compensation, while using the bottom half (< 50%) disables the temperature compensation, even if a thermistor is coupled to the battery pack. the next section provides more detailed information. disable stage 3 : setting the chargecf g1 pin to av dd or 0v disables stage 3. when the chargecf g1 pin is set in this manner, the charging algorithm will never proceed to stage 3. stage 3 is commonly used for lead-acid battery charging but is not typically used for lithium-ion battery charging. enable stage 3 : setting the chargecf g1 pin between 5% to 95% of av dd enables stage 3 charging and sets the stage 3 voltage limit (v s3 ) as a percentage of the stage 2 voltage limit (v s2 ) according to the following formulas. figure 10. recommended current sense filter figure 11. chargecfg1 pin configuration r sense1 c s1 8490 f10 lt8490 cspin csnin r s1 r sense2 c s2 lt8490 cspout csnout r s2 c c2 c c1 8490 f11 100 9590 85 0 5 50 chargecfg1 pin voltage (% of av dd ) 55 95 100 45 temperature compensated charging limits non-temperature compensated charging limits s3 disabled s3 disabled v s3 / v s2 (%) downloaded from: http:///
lt8490 21 8490fa for more information www.linear.com/lt8490 applications information figure 12. battery temperature sensing circuit figure 13. stage 2 voltage limit vs temperature when temperature compensation is enabled 8490 f12 lt8490 gnd av dd tempsense 100nf 11.5k cable to/from charger 10k ntc thermistor thermally coupled with battery pack to charger output at r sense2 when temperature compensated charging and stage 3 are enabled, use: chargecfg1% = 2.67 ? v s3 v s2 ? 0.85 ?? ? ?? ? ?? ?? ?? ?? + 0.55 ?? ?? ?? ?? ? 100% when temperature compensated charging is disabled and stage 3 is enabled, use: chargecfg1% = 2.72 ? 2.67 ? v s3 v s2 ?? ? ?? ? ?? ?? ?? ?? ?? ?? ?? ?? ? 100% where v s3 /v s2 should be between 0.86 to 0.99. for example, to enable temperature compensated charg - ing with v s3 set to 93% of v s2 , choose a divider that puts chargecfg1 at 76% of av dd . for best accuracy use resistors that have a 1% tolerance or better. temperature measurement, compensation and fault the lt8490 can measure the battery temperature using an ntc (negative temperature coefficient) thermistor thermally coupled to the battery pack. the temperature monitoring function is enabled by connecting a 10k, ? = 3380 ntc thermistor from the tempsense pin to ground and an 11.5k (1% tolerance or better) resistor from av dd to tempsense (as shown in figure 12). if battery temperature monitoring is not required, then use a 10k resistor in place of the thermistor. this will indicate to the lt8490 that the battery is always at 25c. the lt8490 monitors the voltage on the tempsense pin to determine the battery temperature and also to detect if the thermistor is connected or not. a tempsense volt - age greater than 96% of av dd (typical) indicates that the thermistor has been disconnected. three charger functions rely on the tempsense information. 1. invalid battery temperature fault : a tempera - ture fault occurs when the battery temperature is outside of the valid range as configured on the chargecf g2 pin (C20c to 50c or 0c to 50c ). the temperature fault condition remains until the temperature returns within C 15 c to 45 c or 5c to 45 c ( 5c of hysteresis). during a temperature fault, charging is halted and the status and fault pins follow the pattern described in table 6. if timer termination is enabled with the chargecf g2 pin, the timer count is paused during the temperature fault and resumes when the fault state is exited. 2. battery voltage temperature compensation : some battery chemistries charge best when the voltage limit is adjusted with battery temperature. lead-acid batteries, in particular, experience a significant change in the ideal charging voltage as temperature changes. if enabled with the chargecf g1 pin, the battery charging voltage and all related voltage thresholds are automati - cally adjusted with battery temperature. as the voltage on the tempsense pin changes, the p wm duty cycle from the fbow pin changes such that the voltage limits of the lt8490 follow the cur ve shown in figure 13. battery temperature (c) C25 96 98 100 102 104 % of v s2 at 25c (%) 106 108 112110 C5 15 35 C15 5 25 40 55 8490 f13 downloaded from: http:///
lt8490 22 8490fa for more information www.linear.com/lt8490 applications information 3. battery disconnect sensing : the lt8490 detects if the battery and thermistor have been disconnected from the charger by monitoring the tempsense pin voltage. when the connection to the battery is severed, as shown by the arrow in figure 12, the connection to the thermistor is also severed and the tempsense voltage rises up to av dd through the 11.5k resis - tor. during the time when the battery is not present, the lt8490 halts charging. the charger automatically restarts the charging at stage 0 when a batter y (along with integrated thermistor or resistor) is sensed through the tempsense pin. charger configuration C chargecfg2 pinthe chargecf g2 pin is a multifunctional pin as shown in figure 14. set this pin using a resistor divider totaling no less than 100k to the av dd pin (see the typical applica - tions section for examples). the voltage on chargecf g2 , as a percentage of a v dd , makes the selections discussed below. avoid setting the divider ratio directly at any of the inflection points on figure 14 (e.g. 5%, 10%, 45%, 50%, 55%, 90% or 95%) limits using the chargecf g2 pin. for more information about the operation of the time limits see the charging time limits section. setting the chargecf g2 pin between 5% to 95% of av dd allows for time limit settings between 0.5 hours to 3 hours for stage 0, 2 hours to 12 hours for stage 1 and 2 combined and 2 hours to 12 hours for stage 3. the stage 0 time limit is always 1/4th of the stage 1 + stage 2 time limit and the stage 3 time limit is always the same length as the stage 1 + stage 2 limit. when choosing a stage 1 + stage 2 time limit of 12 hours, choose a divider ratio ver y close to 7.5% or 92.5%. when choosing a stage 1 + stage 2 time limit of 2 hours, choose a divider ratio very close to 47.5% or 52.5%. for time limits in between, use one of the following formulas. when the wide valid batter y temperature range ( C20c to 50c) is desired use: chargecf g2% = 3.5% ? (t s1s2 C 2) + 55% where t s1s2 is the desired stage 1 + stage 2 time limit in hours between 2.1 and 11.9. when the narrow valid battery temperature range ( 0c to 50c) is desired use: chargecf g2% = 45% C 3.5% ? (t s1s2 C 2) where t s1s2 is the desired stage 1 + stage 2 time limit in hours between 2.1 and 11.9.setting chargecf g2 below 4% (i.e., ground) or above 96% of av dd (i.e., tie to av dd ) disables the time limits, allowing the charging to run indefinitely in lieu of any fault conditions. select the valid battery temperature range : setting the chargecf g2 pin in the top half of the voltage range ( > 50%) selects a wider valid battery temperature range ( C20c to 50c ), while using the bottom half of the voltage range ( < 50%) selects a narrower valid battery temperature range ( 0c to 50c ). generally, lead-acid batteries would use the wide range, while lithium-ion bat - teries would use the narrow range. see the temperature measurement, compensation and fault section for more information about the invalid battery temperature fault. figure 14. chargecfg2 pin voltage settings chargecfg2 pin voltage (% of av dd ) narrow validbattery temp. range wide valid battery temp. range 0.5 2 3 12 time (hrs) no time limitno time limit 0 5 10 45 50 time limits only available in power supply mode 55 stage 0timer stage 1 and 2combined timer and stage 3 timer 90 95 100 8490 f14 enable/disable charging time limits : the lt8490 supports charging time limits only when power supply mode is enabled (see the dc supply powered charging section). when power supply mode is disabled, any finite time limit setting on chargecf g2 is interpreted as no time limit. this section discusses how to configure the time downloaded from: http:///
lt8490 23 8490fa for more information www.linear.com/lt8490 applications information charging time limits charging time limits can be enabled only in power supply mode by properly configuring the chargecf g2 pin (see the charger configuration C chargecf g2 pin section). charging time limits are not recommended for use when a load is present on the battery due to the unpredictable amount of time that may be required to achieve full charge. when enabled, the appropriate timers start at the beginning of stages 0, 1 and 3. if the timer expires while operating in its respective stage or the lt8490 returns to a charging stage after its respective timer has expired, charging stops immediately. as shown in table 5, expiration of a timer is treated as either a fault or as done charging depending on the timer that expired and the configuration of the charger. in any case, when charging stops, the fault or done charg - ing status is indicated on the status and fault pins as described in the status and fault indicators section. table 5. charger conditions and timer expiration results charging stage when timer expires stage 3 enabled? timer used result of timer expiration 0 C stage 0 fault 1 C stage 1 + stage 2 fault 2 C stage 1 + stage 2 fault 3 yes stage 3 done charging stage 2 termination (time limits enabled) : timer expiration in stage 2 causes a fault and charging stops im - mediately with a fault indication on the status and fault pins. if the stage 2 output current drops below c/10 before the timer expires and stage 3 is disabled then charging stops and done charging is indicated on the st a tus pin. stage 2 termination (time limits disabled) : if time limits are disabled, stage 2 can only terminate if stage 3 is also enabled. after charging current falls below c/10, charging will proceed to stage 3. if stage 3 is also disabled then the charger will operate in stage 2 indefinitely unless the battery voltage falls enough for charging to revert back to stage 1. during the indefinite stage 2 charging, the status pin will indicate if stage 2 current is below c/10 or above c/5 (as shown in tables 6 and 7). stage 3 termination conditions : if stage 3 is enabled and time limits are disabled, the lt8490 will remain in stage 3 forcing reduced constant-voltage indefi - nitely unless the batter y voltage falls below 96% of v s3 or charging current rises above c/5 causing the charger to revert back to stage 0. if stage 3 is enabled and time limits are enabled, timer expiration in stage 3 will stop charging and communicate the done charging state through the status pin (as shown in tables 6 and 7). lithium-ion battery charging the lt8490 is well suited to charge lithium-ion batteries. connecting the chargecf g1 and chargecf g2 pins to ground puts the lt8490 into a typical configuration for lithium-ion battery charging ( 0c to 50c valid battery temperature, stage 3 disabled, no temperature compe nsa - tion, no time limits). figure 15 shows a typical lithium-ion charging cycle in this configuration. if no timer termination has been selected, the lt8490 will charge the lithium-ion battery stack to the desired stage 2 voltage limit, maintaining that limit indefinitely. when the charging current is < c/10, the status pin will go high as described in table 6. note: when solar charging a li-ion battery without time limits it is recommended that the stage 2 voltage limit not exceed 95% of the lithium-ion maximum cell voltage. since this configuration can charge indefinitely, follow - ing this guideline keeps the lifetime of the batteries from degrading quickly. figure 15. lithium-ion battery charging cycle 8490 f15 charging time chargingcurrent battery voltage (float) stage 0 trickle charge stage 1 constant current stage 2 constant voltage stage 2 voltage limit maximum charging current (c) downloaded from: http:///
lt8490 24 8490fa for more information www.linear.com/lt8490 applications information figure 17. example waveform for status pin in stage 3 figure 16. lead-acid battery charging cycle 8490 f16 charging time chargingcurrent battery voltage (absorption) (bulk) (float) stage 0 trickle charge stage 1 constant current stage 2 constant voltage stage 3 reduced constant voltage stage 2 voltage limit stage 3 voltage limit maximum charging current (c) lead-acid battery charging the lt8490 can be used to charge lead-acid batteries. setting the chargecf g1 pin to 87.6% of av dd and chargecfg2 pin equal to av dd configures the lt8490 for typical lead-acid battery charging ( C20c to 50c valid battery temperature, stage 3 enabled with v s3 /v s2 = 97.2%, temperature compensated voltage limits, no time limits). figure 16 shows a typical lead-acid charging cycle. if time limits have been disabled, the lt8490 will charge the lead-acid battery stack to the desired stage 3 voltage limit and restart the charging cycle if 1) the battery voltage falls below 96% of the stage 3 voltage limit (v s3 ) or 2) the charging current rises above c/5. 8490 f17 led on led off 3.5s 0.5s a table 6. status and fault led indicators charger status led pulses/ 3.5s, approximate on-time per pulse for more information see section status fault stage 0 1, 10ms off battery charging algorithm stage 1 1, 250ms off battery charging algorithm stage 2 and (stage 3 enabled or time limits enabled or i out rising above c/5) 2, 250ms off battery charging algorithm and charger configuration sections stage 2 and stage 3 disabled and time limits disabled and i out falling below c/10 on off battery charging algorithm and charger configuration sections stage 3 3, 250ms off battery charging algorithm done charging on off charging time limits battery present detection fault 1, 10ms 1, 250ms temperature measurement, compensation and fault invalid battery temperature fault 1, 10ms 2, 250ms temperature measurement, compensation and fault timer expiration fault 1, 10ms 3, 250ms charging time limits battery undervoltage fault 1, 10ms 4, 250ms stage voltage limits status and fault indicators the lt8490 reports charger status through two outputs, the status and fault pins. these pins can be used to drive leds for user feedback. in addition, the status pin doubles as a uart output to send status information to a peripheral device. table 6 describes the led behavior of these pins in relationship to the charger status. while the lt8490 is operating, the status pin toggles on a 3.5 sec (typical) interval as shown in figure 17. the three pulses shown in figure 17 represent the charger operating in stage 3. the status and fault pins pull up to turn the leds on and drive to ground to turn the leds off. downloaded from: http:///
lt8490 25 8490fa for more information www.linear.com/lt8490 applications information driving leds with the status and fault pins the status and fault pins on the lt8490 can be used to drive led indicators. figure 18 shows the simplest configuration for driving leds from these two pins. the status pin can drive up to 2.5ma into an led. choose r dsa to limit the led current to 2.5ma or less when status is driven close to 3.3v . choose r dsb to conduct a current equivalent to the led current when status is driven close to ground and r dsb has ~3.3v across the terminals. d s , in figure 18, conducts ~2.5ma when status is driven high. r dsb conducts ~2.5ma when the status is driven low. the fault pin has a weak pull up in comparison to the status pin (see the typical performance characteristics section). the led current is typically self-limited to less than 1ma by the fault pin driver. r dfb in figure 18 is typically 3.32k and increases the fault led current. when configured as shown in figure 18, the d f led cur - rent should be limited to less than 1.5ma. for driving higher current leds, the circuit in figure 19 can be used. note that the led current for d f is provided by the intv cc regulator in this case. excessive led current can overload the intv cc regulator and/or cause excessive heating in the lt8490. 7.5ma is a good starting point when using this circuit. higher currents can be possible with careful board evaluation. transistor q2 must have a collector-emitter breakdown voltage greater than intv cc . the mmbt3646 has a breakdown voltage of 15v and is well suited for this application.the led current for d s is provided by v in in this case. do not draw current for d s from intv cc since this increases power dissipation in the lt8490 . transistor q1 must have a collector-emitter breakdown greater than v in . the mmbt5550l has a breakdown voltage of 140v and is suitable for most applications. to properly set the resistors shown in figure 19, use the following equations: r e1 ? 2.6 i d r c1 ? i ntvcc ? v f i d ?? ?? ?? ?? r b1 = 50 i d where intv cc is typically 6.35v , v f is the forward voltage of the led (often about 1.7v ) and i d is the desired bias current through the led. figure 19. higher current drive for status/fault leds figure 18. default status/fault led indicators 8490 f18 lt8490 status ldo33 v dd v dd fault r dsb 1.3k r dsa 549 d s d s : osram, lgl29kf2j124z d f : osram, lgl29k-h1j2-1-z r dfa 549 r dfb d f 8490 f19 lt8490 status v in v in intv cc fault r e1 d s q1: mmbt5550lq2: mmbt3646 r c1 r b1 d f q2 q1 downloaded from: http:///
lt8490 26 8490fa for more information www.linear.com/lt8490 applications information figure 20. uart transmission waveform from figure 17 label (a) figure 21. status byte decode status pin uart the status pin also provides a uart (transmit only) communication function. this feature allows for remote monitoring of the lt8490 . immediately after each initial pulse described in table 6 the status pin sends out a synchronizing byte ( 0x 55) followed by a status byte. uart data is transmitted with the lsb first. figure 20 shows the zoomed in region labeled (a) from figure 17. lp: 0 if in low power mode (see the low power mode section)s2/s1/s0: stage description (see table 7) f2/f1/f0: fault description (see table 8) table 7. stage description stage conditions s2 s1 s0 stage 0 C 0 0 0 stage 1 C 0 0 1 stage 2 stage 3 enabled 0 1 0 timers and stage 3 disabled, charging current has risen above c/5 timers and stage 3 disabled, charging current falls below c/10 1 0 0 stage 3 C 0 1 1 done charging C 1 0 1 table 8. fault description fault information f2 f1 f0 no faults present 0 0 0 battery disconnected (thermistor disconnected) 0 0 1 invalid battery t emperature 0 1 0 timer fault 0 1 1 battery undervoltage 1 0 0 if multiple faults are present, the fault listed highest in table 8 is reported through the status and fault pins. 8490 f20 uart start bit sync byte 0x55 status 0x14 lsb msb uart stop bit uart start bit uart stop bit 8490 f20 lsb msb 0 lp s2 s1 s0 f2 f1 f0 the status byte shown in figure 20 has information regard - ing the present charging stage as well as fault informa - tion. the data format for each uart byte is 8 data bits, no parity , with one stop bit. the baud rate is 2400 baud 10% which may require auto baud rate detection, using the sync byte, for proper data reception. figure 21 defines each bit present in the status byte. the status byte always contains an msb of 0. status bytes containing an msb of 1 should be disregarded. downloaded from: http:///
lt8490 27 8490fa for more information www.linear.com/lt8490 applications information automatic charger restart and fault recovery the lt8490 employs many features and checks that may cause the charger to stop until favorable operating condi - tions return. table 9 summarizes the typical cause for the lt8490 to stop charging along with the conditions under which it will automatically restart charging. upon automatic restart all timers are reset except when resuming from an invalid battery temperature fault. table 9. automatic restart conditions cause for charging to stop requirement for restart restart or resume charging done charging stage 3 disabled and v bat drops below 95% of v s2 restart stage 3 enabled and v bat drops below 96% of v s3 restart battery undervoltage fault v bat rises to 35% of v s2 restart stage 0 timeout v bat rises to 70% of v s2 or every hour after stopping (read below) restart stage 1 timeout v bat rises 5% or v bat rises to 98% of v s2 or every hour after stopping (read below) restart stage 2 timeout v bat falls below 66% of v s2 or every hour after stopping (read below) restart invalid battery temperature battery temperature returns within the valid temperature range with 5c hysteresis resume battery disconnected fault re-connect thermistor restart the charger will attempt to restart every hour (typically) after having stopped due to a timeout fault in stage 0, stage 1 or stage 2. configuring the charger in any of the following ways prevents the charger from automatically restarting every hour: 1. stage 3 disabled and narrow battery temperature range selected and temperature compensated battery voltage not selected. 2. not operating in power supply mode. 3. timer limits disabled. shdn pin connection the lt8490 requires 1.234v (typical) on the shdn pin to start-up. a minimum of 5v on v in is also required for proper start-up operation ; therefore, a resistor divider from v in to the shdn pin is used to set this threshold. connect the shdn pin as shown in figure 22 (1% resistor tolerance or better required). figure 22. shdn pin resistor divider 8490 f22 lt8490 gnd v in v in shdn 110k35.7k downloaded from: http:///
lt8490 28 8490fa for more information www.linear.com/lt8490 figure 23. simplified diagram of switches applications information switching configuration C mode pin the lt8490 has two modes of switching behavior con - trolled by the state of the mode pin. tying mode to a voltage above 2.3v (i.e., v dd or intv cc ) configures the part for discontinuous conduction mode (dcm) which allows only positive current flow to the battery. more information about this mode of operation can be found in the lt8705 data sheet. tying the mode pin below 0.4v (i.e. ground) changes the configuration as follows: 1. automatic ccm/dcm mode switching : very large inductor current ripple can lead the lt8490 to operate at high currents while still in dcm. in this case, the m4 switch (highlighted in figure 23) can become hot due to the battery charging current flowing through the body diode of this device. connecting the mode pin low can reduce the m4 heat - ing by activating the continuous conduction threshold mode (cctm). in this mode the average charging cur - rent is monitored by the imon_out pin. the lt8490 will operate in conventional dcm while the batter y charging current, and thus imon_out , is low (below 122mv typically). as the charging current increases, imon_out will eventually rise above ~195mv signal - ing the lt8490 to enter ccm operation that will turn on m4 and reduce heating. while the average charging current will be positive, this mode does allow some negative current flow within each switching cycle. use dcm operation if this behavior is not desired. 2. automatic extv cc regulator disconnect : as discussed in more detail in the lt8705 data sheet, the intv cc pin is regulated to 6.35v from one of two possible input pins, v in or extv cc . the extv cc pin is often connected to the battery allowing intv cc to be regulated from a low voltage supply which minimizes power loss and heating in the lt8490 . however, extv cc should be disconnected from the battery when charging current is low to avoid discharging the battery. when mode is low, the lt8490 automatically forces the intv cc regulator to use v in instead of extv cc for the input supply when charging current becomes low. charging current is monitored on the imon_out pin. when imon_out falls below 122mv (typical) the intv cc regulator uses v in as the input supply. when imon_out rises above ~195mv intv cc will regulate from extv cc if extv cc is also above 6.4v (typical). this same functionality can be achieved when mode is tied high by using the external circuit discussed in the optional extv cc disconnect section. finally, a 305k (typical) resistor is connected from extv cc to ground inside the lt8490 . this resistor can draw current from the battery unless extv cc is disconnected. see the optional extv cc disconnect section for a way to automatically disconnect extv cc when charging current becomes low or charging stops. 8490 f23 v in v out r sense m2 sw1 sw2 l bg1 m1 m3 m4 tg1 bg2 tg2 downloaded from: http:///
lt8490 29 8490fa for more information www.linear.com/lt8490 applications information optional low power mode when current from the solar panel is not high enough to reliably measure the maximum power point, the lt8490 may automatically begin operating in low power mode. low power mode is automatically disabled when operat - ing from a dc supply in power supply mode. otherwise, the low power mode feature is enabled by default and allows the lt8490 to charge a battery under very low light conditions that would otherwise cause the lt8490 to stop charging. low power mode can also be disabled with a method discussed later in this section. in low power mode, the lt8490 momentarily stops charg - ing, allowing the panel voltage to rise. when the panel has sufficiently charged the input capacitor, the lt8490 transfers energy from the input capacitor to the battery while drawing down the panel voltage. this behavior re - peats rapidly, delivering charge to the battery as shown in the panel voltage in low power mode plots in the t ypical performance characteristics section. minimum input capacitance for low power mode : a minimum amount of energy must be transferred from the input capacitor to the battery during each charge transfer cycle. otherwise the battery may be drained instead of being charged. figure 24 shows the minimum input capacitance required when the charger is operating near the 10v minimum input voltage. as the panel volt - age rises, due to increased illumination, more energy is stored in the input capacitor and a corresponding increase of energy is delivered to the battery . carefully check the solar panel voltage for good stability and minimal ripple when operating with low input capacitance. minimum input voltage : with low power mode enabled, the panel voltage must initially exceed 10v (typical C as measured through the vinr pin) before the charger will attempt to charge the battery. if adequate charge is not being delivered to the battery, the charger may temporarily wait for even more input voltage before transferring the input charge to the battery. exiting low power mode : the charger will automati - cally exit low power mode and resume normal charging after adequate input current is detected. the charger typically requires the input current to exceed 2.5% to figure 25. disabling low power mode with resistor r nlp 3% of the maximum input current limit to make a valid power point reading and exit low power mode. the panel voltage may be adjusted as low as 6v when searching for the maximum power point. disabling low power mode : if the minimum input capacitance, or 10v minimum start-up voltage are not suit - able for the application, low power mode can be disabled by including the resistor r nlp = 3.01k as shown in figure 25. when low power mode is disabled, the lt8490 will attempt to charge the battery after 6v or more is detected on the panel. if the input current is too low (typically less than 1.5% of the maximum input current limit) charging is temporarily halted. the lt8490 will attempt to charge the battery on 30 second intervals or when the lt8490 measures a significant rise in the panel voltage. when the lt8490 determines that there is sufficient panel current, normal charging operation will automatically resume. 8490 f25 lt8490 gnd v in v in r daci1 c daci fbirfbin fbiw r nlp 3.01k r daci2 r fbin1 r fbin2 figure 24. minimum input capacitor required for low power mode battery voltage (v) 0 0 50 100 150 200 minimum input capacitance (f) 250 20 40 60 10 30 50 70 80 8490 f24 downloaded from: http:///
lt8490 30 8490fa for more information www.linear.com/lt8490 applications information figure 26. battery discharge when not charging figure 27. optional feedback resistor disconnect circuit optional output feedback resistor disconnect to measure and regulate the battery voltage, the lt8490 uses a resistor feedback network connected to the battery. unless these resistors are disconnected from the battery, they will draw current from the battery even when it is not being charged as seen in figure 26. this may be undesir - able when using small capacity batteries. if desired, the resistors can be automatically disconnected from the battery when charging stops by using the cir - cuit shown in figure 27. this circuit is controlled by the sweno signal from the lt8490 and connects the resistor feedback network when charging is taking place. when charging stops, the network is disconnected and current draw from the battery becomes negligible. 8490 f26 lt8490 r daco1 gnd fbow fbor swen sweno 200k r daco2 fbout r fbout2 v bat +C c daco r fbout1 i drain 8490 f27 r daco1 gnd fbow swen sweno 200k r daco2 r fbout2 q3 optional feedback resistor disconnect circuit z1 (opt.) v bat +C c daco r vgs1 100k to charger out at r sense2 r lim3 26.1k r fbout1 m5 lt8490 fbor fbout selecting m5: this pmos must have a drain to source breakdown voltage greater than the maximum v bat . the zvp3310 f is rated for 100v making it suitable for most applications. selecting q3: this npn must have a collector to emitter breakdown voltage greater than the maximum v bat . the mmbt5550l is also suitable for most applications due to its 140v breakdown rating. selecting r lim3 : using v gson and setting r vgs1 to 100k r lim3 = r vgs1 v gson ?? ? ?? ? ? 2.6v ?? ? ?? ? where v gson is the desired gate to source voltage needed to turn on m5 . if m5 is not properly selected, the on re - sistance may be large enough to cause a significant volt - age drop across the drain-source terminal of this device. check this voltage drop to determine if the application can tolerate this error . selecting z1 : due to the transients that may occur during hot-plugging of a battery, this zener diode is rec - ommended to protect device m5 from excessive gate to sour ce voltage. if using device z1, the reverse breakdown voltage should be selected such that v gson < v z1breakdown < v gsmax where v gsmax is the maximum rated gate to source voltage specified by the device manufacturer. the bzt52c13 has a reverse breakdown voltage of 13v making it suitable for the r lim3 value shown in figure 27. alternate circuit : for lower battery voltages ( < 20v), q3 in figure 27 can saturate. to avoid this, consider con - necting the emitter of q3 directly to ground by removing r lim3 and adding resistor r lim4 to the base of q3 as shown in figure 28. employing the optional feedback resistor disconnect at arbitrarily low battery voltages will be limited by the required gate to source voltage of m5. use the following equation to properly set r lim4 : r lim4 = 91 ? r vgs1 v bat downloaded from: http:///
lt8490 31 8490fa for more information www.linear.com/lt8490 applications information figure 30. ir drop present in battery connection 8490 f29 lt8490 gnd extv cc econ 200k q4 optional extv cc disconnectcircuit m6: zvp3310fq4: mmbt5550l z2: bzt52c13 z2 (opt.) v bat +C 1f r vgs2 100k to charger out at r sense2 r lim4 26.1k 10 m6 optional extv cc disconnect it is often desirable to connect extv cc to the battery to reduce power loss (increase efficiency) and heating in the lt8490 . however, the lt8490 draws current into the ext - v cc pin that can drain the battery when charging currents are low or when charging stops. tying the mode pin low, as discussed in the switching configuration C mode pin section, eliminates most of the current draw from extv cc when the charging current becomes low. however, there is a 305k (typical) path from extv cc to ground through the lt8490 at all times. if mode is tied high or if the 305k load is undesirable, extv cc can be disconnected with the optional circuit shown in figure 29. the lt8490 , via the econ signal, disconnects extv cc from the battery when charging current becomes low. charging current is monitored by measuring the imon_out pin voltage with the ior pin s a/d input. when imon_out falls below 122mv (typical) the econ signal goes low and extvcc is disconnected from the battery. when imon_out rises above 195mv (typical) the econ signal goes high and extv cc is reconnected to the battery. follow the same recommendations and equations from the previous section for choosing components for the optional extv cc disconnect circuit. optional remote battery voltage sensing the lt8490 measures the battery voltage continually during charging. the apparent battery voltage is sensed from ground of the lt8490 to the top of r fbout1 . dur - ing charging, resistance in the battery cables (r cable + / r cable C in figure 30) causes the apparent voltage to be higher than the actual battery voltage by 2 ? v ir . the effects of this cable drop are most significant when charging low voltage batteries at high currents. as an example, a 4 foot battery cable using 14 awg wire can have a voltage drop exceeding 0.5v at 15a of current. note however that the voltage drop, along with the charging current, reduces automatically as the battery approaches full charge. figure 29. optional extv cc disconnect circuit 8490 f29 r daco1 gnd fbow swen sweno 200k r daco2 r lim4 r fbout2 q3 optional feedback resistor disconnect circuit v bat +C c daco r vgs1 100k to charger out at r sense2 r fbout1 m5 lt8490 fbor fbout figure 28. optional low battery voltage feedback resistor disconnect circuit 8490 f30 lt8490 gnd v ir r daco2 c daco fbor fbow fbout r cable + r cable C r daco1 r fbout1 i charge r fbout2 v bat + + C v ir C + C to charger out at r sense2 downloaded from: http:///
lt8490 32 8490fa for more information www.linear.com/lt8490 figure 31. remove (+) and (C) cable v ir measurement errors 8490 f31 lt8490 gnd r daco2 c daco fbor fbow r daco1 r fbout1 intv cc 1f q5 r fbout2 r5 r3 r2 v bat +C to charger out at r sense2 10 d2a d2b d2c r? fbout1 C + lt1636 d3a d3b r4 r cable C r cable + fbout applications information the most significant effects from the v ir voltage drops are as follows: 1. when approaching full charge in stage 2, the v ir er - ror causes the charger to reduce the charging current earlier than otherwise necessar y. this increases the total charging time. 2. terminating at c/10 in stage 2 will occur at a reduced battery voltage equal to c/10 ? (r cable + + r cable C ) which is 10% of the voltage drop at full charging current. 3. the status pin will indicate a transition from stage 1 to stage 2 earlier than would otherwise occur without the cable drop. again, these effects become less significant at higher battery voltages because the charging current is typically lower and the cable drop becomes a smaller percentage of the total battery voltage. using thicker and/or shorter battery cables is the simplest method for reducing these effects. otherwise, the remote battery sensing circuit in figure 31 can correct for these effects. the r cable + measurement error is eliminated by includ - ing an additional (+) terminal sensing cable. the negative cable error is eliminated by subtracting the r cable C drop from the voltage measured at the positive battery terminal using a ( C ) terminal sensing cable, the lt1636, q5 and r5. r fbout , r? fbout and r5 are determined as follows: r ? fbout1 = 0.5 ? r fbout1 v s2 ? 1.211 r ? fbout1 = r fbout1 ? r ? fbout1 ( ) r5 = r ? fbout1 where v s2 is the room temperature stage 2 voltage limit and the solution for r fbout1 was discussed previously in the stage voltage limits section. solutions for determining r daco1 , r daco2 , r fbout2 and c daco are also discussed in the stage voltage limits section. due to its low current draw ( < 1ma) q5 can be a small signal device with a collector-emitter breakdown voltage at least as high as the battery voltage. the mmbt3904 is a good bjt rated to 40v . alternatively, the mmbt5550l is rated for 140v.r3 is for safety in case the (+) battery sensing cable becomes disconnected. r3 prevents overcharging the battery in such an event by creating an alternate path to pull up the r ? fbout1 battery voltage sensing resistor. the r3 resistance should be less than 1% of r fbout1 . select - ing r3 as a 100 resistor is often a good choice. during downloaded from: http:///
lt8490 33 8490fa for more information www.linear.com/lt8490 applications information normal operation the voltage across r3 is about the same as across r cable + . however, r3 may experience voltage up to v s2 -v bat across its terminals if r cable + becomes disconnected. r3 should be selected with an appropriate power rating, often at least 1w.d2a-d2 c protect the charger if the positive charging cable (r cable + ) becomes disconnected while the others remain intact. without the diodes, the output of the charger may overvoltage and become damaged. ba v99 diodes are a good choice and are available in a dual-diode package to minimize board space. note that the diodes limit the maximum r cable + error to 0.3v to 0.5v . if a greater volt - age drop is typical in the positive cable then place more diodes in series. d2 d protects the m5 device by limiting the gate to source voltage when making the remote sense connection. d3a, d3 b and r4 protect the input of the lt1636 from possible voltage extremes at the ( C ) battery terminal sens - ing connection. the dual-diode ba v99 is also suitable in this case. 4.99k is a good value for r4. r2 maintains a negative voltage reference in case r cable C becomes disconnected. selecting r2 as a 100 resistor is often a good choice. during normal operation the voltage across r2 is about the same as across r cable C . however, r2 may experience voltage in excess of v s2 -v bat across its terminals if r cable C becomes disconnected. r2 should be selected with an appropriate power rating, often at least 1w due to the case where the (+) and ( C ) wires of the remote sense circuit are first connected to the battery to address hot plugging issues (see the hot plugging considerations section for more detail). figure 32 shows how to combine the remote sensing circuit (figure 31) and the feedback resistor disconnect (figure 27) for applications that require the most accurate battery voltage sensing and negligible battery drain when charging completes. the r vgs1 resistor can no longer connect to the source of m5 (as in figure 27) since the r vgs1 current would also flow through r ? fbout1 causing an error in the measured battery voltage. figure 31 shows that r vgs1 has been reconnected to the (+) battery sensing terminal. figure 32. how to combine figure 27 and figure 30 8490 f32 lt8490 gnd r daco2 c daco fbor fbow r daco1 r fbout1 m5 r vgs1 100k intv cc 1f q5 r fbout2 r5 r2 v bat +C to charger out at r sense2 10 d2a d2d d2b d2c r? fbout1 C + r3 lt1636 d3a d3b r4 r cable C r cable + swen sweno 200k q3 r lim3 26.1k fbout downloaded from: http:///
lt8490 34 8490fa for more information www.linear.com/lt8490 figure 33. optional dc supply detection circuit 8490 f33 lt8490 d vdc gnd v in v dc to r sense1 q6: 2sd2704k v panel vinr 100k33k 196k8.06k q6 d panel optional dc supply detection circuit a dual input application can be configured where the charger can be supplied by either a solar panel or a dc supply. when powered by a dc supply, the vinr pin must be pulled low to activate power supply mode. in addition, blocking diodes should be incorporated to prevent the sup - plies from back-feeding into each other. the circuit shown in figure 33 shows a way to incorporate those features. as shown in figure 33, when the dc supply is connected the q6 npn pulls vinr below 174mv (typical) to activate the power supply mode of the lt8490 . be sure to choose an npn that can pull vinr below the power supply mode threshold before fully saturating. alternatively, q6 can be replaced with an nmos device with proper care taken to avoid overvoltage of the nmos gate. depending on the current limit settings, diodes d panel and d vdc can incur significant current and heat. con - sider the use of schottky diodes or an appropriate ideal diode such as the ltc4358, ltc4412, ltc4352 , etc. to minimize heating. applications information board layout considerationsfor all power components and board routing associated with the lt8705 portion of the lt8490 , please refer to the lt8705 documentation for which a circuit board layout checklist and drawing is provided.hot plugging considerations when connecting a battery to an lt8490 charger, there can be significant inrush current due to charge equalization between the partially charged battery stack and the charger output capacitors. to a lesser extent a similar effect can occur when connecting an illuminated panel or powered dc supply to the input. the magnitude of the inrush current depends on (1) the battery, panel or supply voltage, (2) esr of the input or output capacitors, (3) initial voltage of the capacitors, and (4) cable impedance. excessive inrush current can lead to sparking that can compromise con - nector integrity and/or voltage overshoot that can cause electrical overstress on lt8490 pins. excessive inrush current can be mitigated by first con - necting the batter y or supply to the charger through a resistive path, followed quickly by a short circuit. this can be accomplished using staggered length pins in a multi-pin connector. this can also be accomplished through the use of the optional circuit shown in figure 31 by first connecting the (+) and ( C ) battery remote sense connections, which allow the charger output capacitors to charge through resistors r2 and r3 . alternatively, consider the use of a hot swap ? controller such as the lt1641, lt4256 , etc. to make a current limited connection.design example in this design example, the lt8490 is paired with a 175w/5.4a panel (v max < 53v ) and a 12v flooded lead- acid battery. the desired maximum battery charging current (c) is 10a with a trickle charge current of 2.5a (c/4). charger settings are as follows : C20c to 50c valid battery temperature range, temperature compensated charging limits, no time limits and stage 3 is enabled with v s3 /v s2 = 97.2%. in this example resistors are rounded to the nearest standard value. if better accuracy is required then multiple resistors in series may be required. downloaded from: http:///
lt8490 35 8490fa for more information www.linear.com/lt8490 ? with r fbout2 set at 20k and a desired stage 2 voltage limit of 14.2v , the top output feedback resistor, r fbout1 , is calculated according to the following equation: r fbout1 = r fbout2 ? v s2 ? 1.2411.211 ? 0.128 ?? ? ?? ? ? 1 ?? ? ?? ? = 20k ? 14.2 ? 1.2411.211 ? 0.128 ?? ? ?? ? ? 1 ?? ? ?? ? = 234,684 choose r fbout1 = 237k which is the closest standard value resistor. ? following the calculation of r fbout1 , solve for r daco1 , r daco2 and c daco according to the following formulas : r daco2 = r fbout1 ? r fbout2 ? 0.833 r fbout2 ? v s2 ? 1.2411.211 ?? ? ?? ? ? r fbout2 ? r fbout1 = 234,684 ? 20k ? 0.833 20k ? 14.2 ? 1.2411.211 ?? ? ?? ? ? 20k ? 234,684 = 107,556 choose r daco2 = 107k which is the closest standard value resistor. r daco1 = (0.2 ? r daco2 ) = 0.2 ? 107,556 = 21,511 choose r daco1 = 21.5k which is the closest standard value resistor. c daco = 1 500 ? r daco1 f = 1 500 ? 21,511 f = 93nf applications information ? using the standard value resistors calculated above, the v x3 , n 1 and n 2 checking equations yield the following : v x3 = 14.31v n 1 = 1.22 n 2 = 0.804 ? in order to find a resistor combination that yields v x3 closer to the desired 14.2v , r fbout2 is increased to the next higher standard value and the above calculations are repeated. ? iterations of the previous step are performed that include adjustments to r fbout1 , r daco1 and r daco2 until the following standard value feedback resistors were chosen: r fbout1 = 274k r fbout2 = 23.2k r daco1 = 26.1k r daco2 = 124k c daco = 0.082f where : v x3 = 14.27v n 1 = 1.22 n 2 = 0.805 ? with the output feedback network determined, use v max and solve for the input resistor feedback network according to the following formulas: r fbin1 = 100k ? 1 + 4.47v v max ? 6v ?? ? ?? ? 1 + 5.593v v max ? 6v ?? ? ?? ? ?? ?? ? ? ?? ?? ? ? = 100k ? 1 + 4.47v 53v ? 6v ?? ? ?? ? 1 + 5.593v 53v ? 6v ?? ? ?? ? ?? ?? ? ? ?? ?? ? ? = 97,865 downloaded from: http:///
lt8490 36 8490fa for more information www.linear.com/lt8490 applications information the closest standard value for r fbin1 is 97.6k. r daci2 = 2.75 ? r fbin1 v max ? 6v ?? ? ?? ? = 2.75 ? 97,865 53v ? 6v ?? ? ?? ? = 5,726 choose r daci2 = 5.76k which is the closest standard value. r fbin2 = 1 1 100k ? r fbin1 ?? ? ?? ? ? 1 r daci2 ?? ? ?? ? = 1 1 100k ? 97,865 ?? ? ?? ? ? 1 5,726 ?? ? ?? ? = 3,404 choose r fbin2 = 3.4k which is the closest standard value. r daci1 = 0.2 ? r daci2 = 0.2 ? 5,726 = 1,145 choose r dac1 = 1.1k which is the closest standard value. c daci = 1 1000 ? r daci1 f = 1 1000 ? 1,145 f = 873nf ? similar to the output feedback resistors, the final input feedback resistors were chosen to be standard values using an iterative process. the v x1 and v x2 equations in the input voltage sensing and modulation network section were used to validate the selections: r fbin1 = 93.1k r fbin2 = 3.24k r daci1 = 1.05k r daci2 = 5.49k c daci = 1f where : v x1 = 6v v x2 = 53v ? the 10a maximum charge current limit and 2.5a trickle charge current limit are set by choosing r sense2 , r imon_out and r iow using the following formulas: r sense2 = 0.0497 i out(max) = 0.0497 10 ? 5m r imon _ out = 1208 i out(maxs0) ? r sense2 = 1208 2.5 ? 5m = 96.64k where the nearest standard value is 97.6k. r iow = 24.3k ? r imon _ out r imon _ out ? 24.3k = 24.3k ? 47.6k 97.6k ? 24.3k = 32,356 where the nearest standard value is also 32.4k. downloaded from: http:///
lt8490 37 8490fa for more information www.linear.com/lt8490 applications information ? the input current limit is set by properly choosing r sense1 . in this example, the panel can deliver up to 5.4a. choosing a margin of 30% yields: r sense1 = 0.0505 i in(max) = 0.0505 1.3 ? 5.4 = 7.2m ? to enable temperature compensated charging limits and allow a stage 3 regulation voltage of 97.2% of stage 2, use v s3 /v s2 = 0.972 in the following equation : chargecfg1% = 2.67 ? v s3 v s2 ? 0.85 ?? ? ?? ? + 0.55 ?? ? ?? ? ? 100% chargecfg1% = 87.6% standard resistor values of 90.9k (from chargecf g1 to ground) and 13k (from av dd to chargecf g1 ) can be used to set chargecfg1. ? to set no time limits with a C20c to 50c valid battery temperature range requires chargecf g2 to be tied to av dd . ? for greater charging voltage accuracy, it is recom - mended that 0.1% tolerance resistors be used for the output feedback resistor network. ? please reference the lt8705 data sheet for completing the remaining power portions of the lt8490. downloaded from: http:///
lt8490 38 8490fa for more information www.linear.com/lt8490 applications information figure 34. 27.4v lithium-ion polymer battery charger c in2 2.2f2 8490 f34 3.3nf 3.3nf 10 csp bg1 sw1 boost1 tg1 csn gnd bg2 sw2 boost2 tg2 cspout csnout extv cc fbor fbout fbow 10 6m l1 10h 2 c out3 10f2 c out2 10f2 c in3 2.2f2 c out1 150f 100 220nf 220nf d b1 24.3k m3 gat ev cc 442k v dd av dd c in4 2.2f d b2 gat ev cc tenergy 31417li-ion polymer 10ah 7s1p load +C ?w 7m ?w 10m 470nf +C 549 v oc < 53v solar panel 2 m1 m4 18.7k tempsense srvo_fbin srvo_iin srvo_fbout srvo_iout econ swen sweno chargecfg1 chargecfg2 rtss iir imon_in iow imon_out ior status fault sync v c clkdet clkout lt8490 549 df ds 102k ldo33 csnincspin v in gatev cc gatev cc mode intv cc fbin fbirfbiw vinr shdn 4.7f 82nf 1f 100nf 10 10 200k 4.7f 2 196k 8.06k 93.1k3.24k 110k35.7k 4 5.49k 215k 53.6k 1.3k 3.32k 1.05k 0.82f 100nf 10nf 27.4v stage 2 (float) charge voltage (v s2 ) stage 3 disabled5a charging current limit 2a trickle current limit 7.2a input current limit 53v maximum panel voltage (v max ) no timer limitstemperature compensation disabled 202khz switching frequency example solar panel: sharp nt-175uc1 175w m1, m2: infineon bsc028n06nsm3, m4: infineon bsc059n04lsg l1: 10h coilcraft ser2915h-103kl d b1 , d b2 : central semi cmmr1u-02 c in1 : 33f, 63v, suncon 63hvh33m c in2 , c in3 , c in4 : 2.2f, 100v, avx 12101c225kat2a c out1 : 150f, 50v panasonic eeu-fr1h151 c out2 , c out3 : 10f, 35v, murata grm32er7ya106ka12 c out4 : 1f, 50v, tdk cga6l2x7r1h105k c cspout : 100nf, 50v, avx 08055c10 68nf 10k 3.01k 40.2k 220pf 8.2nf 21k 60.4k 10nf 470nf m2 11.5k 10k av dd c in1 33f3 c out4 1f c cspout 100nf downloaded from: http:///
lt8490 39 8490fa for more information www.linear.com/lt8490 applications information 56.8v lead-acid battery charger (four 12v batteries in series) c in2 2.2f2 8490 ta02 10nf 10nf 10 csp bg1 sw1 boost1 tg1 csn gnd bg2 sw2 boost2 tg2 cspout csnout extv cc fbor fbout fbow 10 6m l1 15h ?w 10m c out2 4.7f2 c out3 4.7f2 c in3 2.2f2 c out1 220f 100 220nf 220nf d b1 22.6k m3 gat ev cc 1m v dd av dd c in4 2.2f d b2 gat ev cc floodedlead acid load +C ?w 5m 470nf +C 549 v oc < 80v solar panel m1 m4 20k tempsense srvo_fbin srvo_iin srvo_fbout srvo_iout econ swen sweno chargecfg1 chargecfg2 rtss iir imon_in iow imon_out ior status fault sync v c clkdet clkout lt8490 549 df ds 115k ldo33 csnincspin v in gatev cc gatev cc mode intv cc fbin fbirfbiw vinr shdn 4.7f 0.1f 1f 100nf 10 10 90.9k 200k 4.7f 2 196k 8.06k 133k3.09k 110k35.7k 4 4.87k 301k 53.6k 1.3k 13k 3.32k 1.05k 1f 100nf 8.2nf 56.8v stage 2 (absorption) charge voltage (v s2 ) at 25c 55.2v stage 3 (float) charge voltage (v s3 ) at 25c 5a charging current limit1.25a trickle current limit 11.4a input current limit 80v maximum panel voltage (v max ) no timer limitstemperature compensation enabled C20c to 50c battery temperature range 145khz switching frequency example solar panel: sharp nt-175uc1 175w, sharp nu-u235f3 235w m1: infineon bsc046n10nsm2: infineon bsc109n10ns m3, m4: infineon bsc057n08ns l1: 15h coilcraft ser2915h-153kl d b1 , d b2 : central semi cmmr1u-02 c in1 , c out1 : 220f, 100v, united chemi-con ekze101ell221mk255 c in2 , c in3 , c in4 : 2.2f, 100v, avx 12101c225kat2a c out2 , c out3 : 4.7f, 100v, tdk c4532x7s2a475m230kb c out4 : 1f, 100v avx 12101c105kat2a c cspout : 100nf, 50v, avx 08055c10 68nf 11.3k 3.01k 32.4k 220pf 10nf 21k 97.6k 10nf 470nf m2 11.5k 10kat 25c ? = 3380 ntc av dd av dd c in1 220f c out4 1f c cspout 100nf downloaded from: http:///
lt8490 40 8490fa for more information www.linear.com/lt8490 package description ukj package variation: ukj64(58) 64(58)-lead plastic qfn (7mm 11mm) (reference ltc dwg # 05-08-1922 rev ?) 11.00 0.10 7.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) 63 12 bottom viewexposed pad 11.00 0.10 9.50 ref 0.75 0.05 0.25 0.05 (ukj64(58)) qfn 0412 rev ? 0.50 bsc 0.50 ref 0.200 ref 0.00 C 0.05 apply solder mask to areas that are not soldered 5.50 ref 0.325 ref 0.40 0.10 0.50 bsc 0.45 9.50 ref 5.50 ref 11.50 0.05 10.10 0.05 7.50 0.05 0.70 0.05 1.50 0.05 9.38 0.05 3.60 0.05 3.83 0.25 0.05 packageoutline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer 64 53 5244 40 35 33 31 27 25 21 20 3.60 0.10 3.83 0.10 0.45 0.10 9.38 0.10 1.50 0.10 1.20 0.10 1.80 0.05 please refer to http://www.linear.com/product/lt8490#packaging for the most recent package drawings. downloaded from: http:///
lt8490 41 8490fa for more information www.linear.com/lt8490 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/15 changed diode type symbol. modified the block diagram. 1, 38, 39, 42 11 downloaded from: http:///
lt8490 42 8490fa for more information www.linear.com/lt8490 ? linear technology corporation 2014 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8490 lt 1115 rev a ? printed in usa related parts typical application part number description comments lt3652/lt3652hv power tracking 2a battery charger for solar power v in range = 4.95v to 32v (lt3652), 4.95v to 34v (hv), mppc ltc4000-1 high voltage, high current controller for battery charger with mppc v in and v out range = 3v to 60v, mppc ltc4020 55v v in /v out buck-boost multi-chemistry battery charging controller li-ion and lead-acid algorithms, mppc 14.2v flooded lead-acid battery charger c in2 2.2f2 8490 ta03 3.3nf 3.3nf 10 csp bg1 sw1 boost1 tg1 csn gnd bg2 sw2 boost2 tg2 cspout csnout extv cc fbor fbout fbow 10 5m l1 15h 2 c out2 10f2 c out3 10f2 c in3 2.2f2 c out1 150f 220nf 220nf d b1 26.1k m3 gat ev cc 274k v bat v dd av dd c in4 2.2f d b2 gat ev cc flooded lead acid load +C ?w 7m 1w 5m 470nf +C 549 v oc < 53v solar panel 2 m1 m4 23.2k tempsense srvo_fbin srvo_iin srvo_fbout srvo_iout econ swen sweno chargecfg1 chargecfg2 rtss iir imon_in iow imon_out ior status fault sync v c clkdet clkout lt8490 549 df ds 124k ldo33 csnincspin v in gatev cc gatev cc mode intv cc fbin fbirfbiw vinr shdn 4.7f 10k at 25c ? = 3380 ntc 0.082f 1f 100nf 10 10 200k 90.9k 4.7f 2 196k 8.06k 93.1k3.24k 110k35.7k 4 5.49k 249k 53.6k 1.3k av dd 3.32k 1.05k 1f 100nf 4.7nf 14.27v stage 2 (absorption) charge voltage (v s2 ) at 25c 13.87v stage 3 (float) charge voltage (v s3 ) at 25c 10a charging current limit2.5a trickle current limit 7.2a input current limit 53v maximum panel voltage (v max ) no timer limitstemperature compensation enabled C20c to 50c battery temperature range 175khz switching frequency example solar panel: sharp nt-175uc1 175w m1, m2: infineon bsc028n06nsm3, m4: infineon bsc042n03lsg l1: 15h coilcraft ser2915h-153kl d b1 , d b2 : central semi cmmr1u-02 c in1 : 33f, 63v, suncon 63hvh33m c in2 , c in3 , c in4 : 2.2f, 100v, avx 12101c225kat2a c out1 : 150f, 35v nichicon upj151mpd6td c out2 , c out3 : 10f, 35v, murata grm32er7ya106ka12 c out4 : 1f, 25v avx 12063c105kat2a 68nf 8.45k 3.01k 32.4k 470pf 10nf 21k 97.6k 8.2nf 470nf m2 11.5k 13k av dd c in1 33f3 c out4 1f downloaded from: http:///

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